1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to methods of forming wiring to a transistor and a related transistor.
2. Background Art
In current field effect transistor (FET) technology, contacts between FETs and a first metal layer are becoming a significant problem for continued scaling. In particular, in order for contacts to reach source/drain regions between the gates of adjacent FETs, they must be extremely tall. Consequently, they must be fabricated with extremely steep sidewalls, very high aspect ratios, very tiny cross sectional area, and very tight alignment tolerances in order to squeeze them into the small space available between the gates. Furthermore, each contact has a significant amount of parasitic capacitance between itself and the gate, which degrades the FET performance. In addition, the contacts have high and potentially quite varied resistance due to their small size and high aspect ratio, which also degrades the FET performance. The contacts also require holes in the stress/strain generating layers, relaxing some of the stress/strain and decreasing FET performance. In addition, advanced transistor design may include new structures (e.g., FINFETs, Trigates, etc.) that require even higher aspect ratio contacts. Overall, processing of these devices is much more complicated and new methods to simplify their fabrication are desirable.
In creating highly interconnected three-dimensional (3D) IC chips, it is advantageous to bond multiple layers of circuitry together from different silicon substrates. This can be done either front-to-front, or front-to-back. Front-to-front bonding is desirable because it eliminates the need for an extra handle wafer, but contacting the devices generally requires an extra layer of wiring between the two device layers. The extra layer adds complexity, costs and size.